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2011-02-01 rev.3.0 TPCL4203 1 mosfets silicon n-channel mos (u-mos ) TPCL4203 TPCL4203 TPCL4203 TPCL4203 1. 1. 1. 1. applications applications applications applications ? dedicated to single-cell lithium-ion secondary battery applications note: the product(s) described herein should not be used for any other application. 2. 2. 2. 2. features features features features (1) small, thin package (2) low source-source on-resistance: r ss(on) = 27 m ? (typ.) (v gs = 4.5 v) (3) low leakage current: i sss = 10 a (max) (v ss = 24 v) (4) enhancement mode: v th = 0.5 to 1.2 v (v ss = 10 v, i s = 200 a) (5) common drain 3. 3. 3. 3. packaging and internal circuit packaging and internal circuit packaging and internal circuit packaging and internal circuit 1: source 1 2: gate 1 3: gate 2 4: source 2 4. 4. 4. 4. absolute maximum ratings (note) (t absolute maximum ratings (note) (t absolute maximum ratings (note) (t absolute maximum ratings (note) (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics source-source voltage gate-source voltage source current (dc) source current (pulsed) power dissipation power dissipation channel temperature storage temperature (t = 10 s) (t = 10 s) (note 1) (note 1) (note 2), (note 4) (note 3), (note 4) symbol v sss v gss i s i sp p d p d t ch t stg rating 24 12 6 24 0.50 1.65 150 -55 to 150 unit v a w w note: using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook ("handling precautions"/"derating concept and methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc). chiplga
2011-02-01 rev.3.0 TPCL4203 2 5. 5. 5. 5. thermal characteristics thermal characteristics thermal characteristics thermal characteristics characteristics channel-to-ambient thermal resistance channel-to-ambient thermal resistance (t = 10 s) (t = 10 s) (note 2), (note 4) (note 3), (note 4) symbol r th(ch-a) r th(ch-a) max 250 75.8 unit /w /w note 1: ensure that the channel temperature does not exceed 150 . note 2: device mounted on a glass-epoxy board (a), figure 5.1 note 3: device mounted on a glass-epoxy board (b), figure 5.2 note 4: equal voltage applied to fet1 and fet2. fig. fig. fig. fig. 5.1 5.1 5.1 5.1 device mounted on a glass-epoxy board (a) device mounted on a glass-epoxy board (a) device mounted on a glass-epoxy board (a) device mounted on a glass-epoxy board (a) fig. fig. fig. fig. 5.2 5.2 5.2 5.2 device mounted on a glass-epoxy board (b) device mounted on a glass-epoxy board (b) device mounted on a glass-epoxy board (b) device mounted on a glass-epoxy board (b) note: this transistor is sensitive to electrostatic discharge and should be handled with care.
2011-02-01 rev.3.0 TPCL4203 3 6. 6. 6. 6. safety precautions safety precautions safety precautions safety precautions this section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury to human body and damage to property, and to ensure safe and correct use of our products. please be sure that you understand the meanings of the labels and graphic symbols described below before you move on to the detailed descriptions of the precautions, and comply with the precautions stated.
2011-02-01 rev.3.0 TPCL4203 4 7. 7. 7. 7. electrical characteristics electrical characteristics electrical characteristics electrical characteristics 7.1. 7.1. 7.1. 7.1. static characteristics (t static characteristics (t static characteristics (t static characteristics (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics gate leakage current source cut-off current source-source breakdown voltage gate threshold voltage source-source on-resistance (note 5) (note 5) (note 5) (note 5) (note 6) symbol i gss i sss v (br)sss v (br)ssx v th r ss(on) test condition v gs = 12 v, v ds = 0 v v ss = 24 v, v gs = 0 v i s = 10 ma, v gs = 0 v i s = 10 ma, v gs = -12 v v ss = 10 v, i s = 200 a v gs = 2.5 v, i s = 3 a v gs = 3.1 v, i s = 3 a v gs = 4.0 v, i s = 3 a v gs = 4.5 v, i s = 3 a min 24 12 0.5 30 26 23 22 typ. 42 33 29 27 max 0.1 10 1.2 55 46 38 36 unit a v m ? 7.2. 7.2. 7.2. 7.2. dynamic characteristics (t dynamic characteristics (t dynamic characteristics (t dynamic characteristics (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics input capacitance reverse transfer capacitance output capacitance switching time (rise time) switching time (turn-on time) switching time (fall time) switching time (turn-off time) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) (note 5) symbol c iss c rss c oss t r t on t f t off test condition v ss = 10 v, v gs = 0 v, f = 1 mhz see figure 7.2.1. min typ. 685 100 145 85 120 210 370 max unit pf ns fig. fig. fig. fig. 7.2.1 7.2.1 7.2.1 7.2.1 switching time test circuit switching time test circuit switching time test circuit switching time test circuit 7.3. 7.3. 7.3. 7.3. gate charge characteristics (t gate charge characteristics (t gate charge characteristics (t gate charge characteristics (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics total gate charge (gate- source plus gate-drain) gate-source charge 1 (note 5) (note 5) symbol q g q gs1 test condition v ss(ps) 19 v, v gs = 5 v, i s = 6 a min typ. 10 1.7 max unit nc 7.4. 7.4. 7.4. 7.4. source-source characteristics (t source-source characteristics (t source-source characteristics (t source-source characteristics (t a a a a = 25 = 25 = 25 = 25 unless otherwise specified) unless otherwise specified) unless otherwise specified) unless otherwise specified) characteristics diode forward voltage (note 7) symbol v ssf test condition i sr = 3 a, v gs = 0 v min typ. max -1.2 unit v note 5: fet1 is measured with the gate and source pins of fet2 shorted. fet2 is measured with the gate and source pins of fet1 shorted. note 6: measured with the indicated gate-to-source voltage (v gs ) applied to both fet1 and fet2. note 7: fet1 is measured with 4.5 v applied between the gate and source pins of fet2. fet2 is measured with 4.5 v applied between the gate and source pins of fet1.
2011-02-01 rev.3.0 TPCL4203 5 8. 8. 8. 8. marking marking marking marking fig. fig. fig. fig. 8.1 8.1 8.1 8.1 marking marking marking marking
2011-02-01 rev.3.0 TPCL4203 6 9. 9. 9. 9. mounting condition mounting condition mounting condition mounting condition this device should be soldered onto a pc board with up to two reflow passes at the recommended reflow conditions. the second reflow process should be performed within two weeks after the first reflow process. 9.1. 9.1. 9.1. 9.1. using infrared reflow using infrared reflow using infrared reflow using infrared reflow (1) it is recommended the top and bottom heating method with long or medium infrared rays. (see figure 9.1.1.) (2) figure 9.1.2 shows the recommended temperature profile for using eutectic solder. figure 9.1.3 shows the recommended temperature profile for using lead (pb)-free solder. complete the infrared ray reflow process with a maximum package surface temperature of 260 , within 30 to 50 seconds when a package surface temperature is 230 or higher (see figure 9.1.3). fig. fig. fig. fig. 9.1.1 9.1.1 9.1.1 9.1.1 heating the top and bottom with long or medium infrared rays heating the top and bottom with long or medium infrared rays heating the top and bottom with long or medium infrared rays heating the top and bottom with long or medium infrared rays fig. fig. fig. fig. 9.1.2 9.1.2 9.1.2 9.1.2 eutectic recommended temperature eutectic recommended temperature eutectic recommended temperature eutectic recommended temperature profile profile profile profile fig. fig. fig. fig. 9.1.3 9.1.3 9.1.3 9.1.3 lead (pb)-free recommended lead (pb)-free recommended lead (pb)-free recommended lead (pb)-free recommended temperature profile temperature profile temperature profile temperature profile 9.2. 9.2. 9.2. 9.2. using hot air reflow using hot air reflow using hot air reflow using hot air reflow for an example of a recommended temperature profile, refer to figures 9.1.2 and 9.1.3.
2011-02-01 rev.3.0 TPCL4203 7 9.3. 9.3. 9.3. 9.3. mechanical stress mechanical stress mechanical stress mechanical stress this device is very small and thin. excessive mechanical stress may damage the package and/or chip. to avoid damage to the device, the distortion factor should be kept below 2000 or within the shaded area in figure 9.3.1. keep in mind that the stress applied to the device varies, depending on the shape, material, trace patterns, parts layout and other conditions of the pc board. thus the integrity of the device should be tested on the actual application board. in addition, the end product should provide adequate headroom above the top (marking) side of the device so that no mechanical stress will be applied to it. the distortion factor ( ) is given by: = 6 h s/ (l l), h: board thickness, s = bend, l = support-to-support distance fig. fig. fig. fig. 9.3.1 9.3.1 9.3.1 9.3.1 support-to-support distance vs. bending support-to-support distance vs. bending support-to-support distance vs. bending support-to-support distance vs. bending 9.4. 9.4. 9.4. 9.4. test method test method test method test method test method (reference standard jeita ed-4702a): the test board is placed on supports with the device face-down. the supports are placed with a distance of 24 mm as shown in figure 9.4.1 below. stress is applied to the test board as shown in figure 9.4.2. test board: fr-4 glass epoxy board measuring 30.8 mm 5 mm 0.6 mm a rigid pc board with a thickness of 0.4 mm or more should be used for actual applications. fig. fig. fig. fig. 9.4.1 9.4.1 9.4.1 9.4.1 placement placement placement placement fig. fig. fig. fig. 9.4.2 9.4.2 9.4.2 9.4.2 during testing during testing during testing during testing
2011-02-01 rev.3.0 TPCL4203 8 10. 10. 10. 10. characteristics curves (note) characteristics curves (note) characteristics curves (note) characteristics curves (note) fig. fig. fig. fig. 10.1 10.1 10.1 10.1 i i i i s s s s - v - v - v - v ss ss ss ss (note 6) (note 6) (note 6) (note 6) fig. fig. fig. fig. 10.2 10.2 10.2 10.2 i i i i s s s s - v - v - v - v ss ss ss ss (note 6) (note 6) (note 6) (note 6) fig. fig. fig. fig. 10.3 10.3 10.3 10.3 i i i i s s s s - v - v - v - v gs gs gs gs (note 5) (note 5) (note 5) (note 5) fig. fig. fig. fig. 10.4 10.4 10.4 10.4 v v v v ss ss ss ss - v - v - v - v gs gs gs gs (note 6) (note 6) (note 6) (note 6) fig. fig. fig. fig. 10.5 10.5 10.5 10.5 r r r r ss(on) ss(on) ss(on) ss(on) - i - i - i - i s s s s (note 6) (note 6) (note 6) (note 6) fig. fig. fig. fig. 10.6 10.6 10.6 10.6 r r r r ss(on) ss(on) ss(on) ss(on) - t - t - t - t a a a a (note 6) (note 6) (note 6) (note 6)
2011-02-01 rev.3.0 TPCL4203 9 fig. fig. fig. fig. 10.7 10.7 10.7 10.7 i i i i sr sr sr sr - v - v - v - v ss ss ss ss (note 7) (note 7) (note 7) (note 7) fig. fig. fig. fig. 10.8 10.8 10.8 10.8 capacitance - v capacitance - v capacitance - v capacitance - v ss ss ss ss (note 5) (note 5) (note 5) (note 5) fig. fig. fig. fig. 10.9 10.9 10.9 10.9 v v v v th th th th - t - t - t - t a a a a (note 5) (note 5) (note 5) (note 5) fig. fig. fig. fig. 10.10 10.10 10.10 10.10 dynamic input/output characteristics dynamic input/output characteristics dynamic input/output characteristics dynamic input/output characteristics (note 5) (note 5) (note 5) (note 5) fig. fig. fig. fig. 10.11 10.11 10.11 10.11 p p p p d d d d - t - t - t - t a a a a (note 4) (note 4) (note 4) (note 4) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum)
2011-02-01 rev.3.0 TPCL4203 10 fig. fig. fig. fig. 10.12 10.12 10.12 10.12 r r r r th th th th - t - t - t - t w w w w (note 4) (note 4) (note 4) (note 4) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) fig. fig. fig. fig. 10.13 10.13 10.13 10.13 safe operating area (note 4) safe operating area (note 4) safe operating area (note 4) safe operating area (note 4) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) (guaranteed maximum) note: the above characteristics curves are presented for reference only and not guaranteed by production test, unless otherwise noted.
2011-02-01 rev.3.0 TPCL4203 11 package dimensions package dimensions package dimensions package dimensions unit: mm weight: 0.00147 g (typ.) package name(s) toshiba: 2-2w1s nickname: chiplga
2011-02-01 rev.3.0 TPCL4203 12 restrictions on product use restrictions on product use restrictions on product use restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "product") without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, product can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs including the product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. toshiba assumes no liability for customers' product design or applications. toshiba assumes no liability for customers' product design or applications. toshiba assumes no liability for customers' product design or applications. ? product is intended for use in general electronics applications (e.g., computers, personal equipment, office equipment, measuring equipment, industrial robots and home electronics appliances) or for specific applications as expressly stated in this document. product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/ or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact ("unintended use"). unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance-related fields. do not use product for unintended use unless specifically permitted in this document. ? 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